1. Field of the Invention
The present invention is directed towards a converter having lossless snubbing components including inductors which minimize "shoot through" currents which would occur due to the reverse recovery time of diodes used in the converter and which also include elements for recovering the power stored in the anti-shoot through inductors. In the presently preferred embodiment, the invention is used in connection with a DC to DC resonant current driven regulator. The invention can be used, however, in connection with more conventional voltage driven or current driven converters.
2. Description of the Prior Art
The present invention is particularly useful in connection with the current drive resonant converter of copending application Ser. No. 417,465, filed Sept. 13, 1982 now U.S. Pat. No. 4,475,149, issued Oct. 2, 1984. The disclosure of this application is incorporated herein by reference.
The preferred structure of the resonant current driven DC/DC converter regulator of the foregoing invention is illustrated in FIG. 1A. As shown therein, the resonator 10 includes an input inverter circuit 12 which converts a DC input signal Es into an AC signal, an LC circuit 14 across which the a.c. signal is applied, and an output circuit 16 which converts the AC voltage appearing across the primary winding W1 of transformer T3 into a DC voltage Eo. While the input inverter circuit may take any form, it preferably includes four high-speed mosfet transistors Q1-Q4, each of which inherently includes a respective substrate diode CR1-CR4 across its drain end source.
The switching operation of transistors Q1-Q4 is controlled by a control signal generating circuit 18 whose structure is illustrated in detail in copending application Ser. No. 417,465. It is sufficient to note that the control signal generating circuit generates control signals CP1, CP2 which are applied to the primary windings of transformers T1 and T2, respectively, and control the operation of transistors Q1-Q4.
The control signals CP1, CP2 take the form illustrated in lines D and A, respectively, of FIG. 2. As shown therein, control signal CP2 is a square wave having a period Ts and a frequency fs=1/Ts. This frequency is the switching frequency of transistors Q3 and Q4 and define the frequency of the a.c. waveform appearing across the primary winding of transformer T3.
The control signal CP2 is applied to the primary winding PW2 of transformer T2 and induces control signals CP2' and CP2' in the secondary windings SW3 and SW4, respectively, of transofrmer T2. These signals are applied to the respective gates of transistors Q3 and Q4 and turn these transistors on during alternate half periods of the switching cycle.
The control signal CP1 takes the general form illustrated in line D of FIG. 4 and includes a positive going pulse during a portion of the first half of each period Ts and a negative going pulse during a portion of the second half of each period Ts. As will be explained in greater detail below, the duration and position with respect to control signal CP2 of each positive and negative going pulse of the control signal CP1 is varied by the control circuit 18 to regulate the magnitude of the output voltage Eo. The control signal CP1 is applied to the primary winding PW1 of transformer T1 and induces control signals CP1' and CP1' in the secondary windings SW1, SW2, respectively, of transformer T1. These control signals are applied to respective gates of transistors Q1 and Q2 and cause transistors Q1 and Q2 to turn on during selected portions of alternating half cycles of the switching period Ts. As will be described in below, the timing of the leading and trailing edges of each pulse set CP1', CP1' controls the magnitude and duration of current pulses applied to output capacitor C1 of output circuit 16 and thereby controls the magnitude of the output voltage Eo.
LC circuit 14 defines a resonant circuit having a resonant frequency fr which is greater than the switching frequency fs defined by control signal CP2. The resonant frequency fr is preferably approximately 21/2 times the switching frequency fs and may be defined as: ##EQU1## wherein L1 is the inductance of inductor L1 and Ceq is the capacitance of the equivalent capacitor Ceq appearing across the primary winding of transformer T3. Equivalent capacitor Ceq is defined by the stray capacitance on both the primary and secondary windings of transformer T3 and any capacitance appearing in the output circuit 16 on the transformer side of rectifier bridge 20 which is reflected back to the primary winding of transformer T3. Since the stray capacitance alone is not normally sufficiently high to cause the resonant frequency fr to reach the desired value, a capacitor C2 is placed across the secondary winding of transformer T3. This capacitor is reflected to the primary winding of transformer T3 and forms part of the equivalent capacitance Ceq. Alternatively, the capacitor C2 may be placed across the primary winding of transformer T3.
The operation of power circuit 10 can best be understood with reference to the waveforms of FIG. 2 and the circuit diagrams of FIGS. 1A-1D. At the beginning of each switching cycle (at time t0 of FIG. 2), capacitor Ceq is charged to -Ep volts where: ##EQU2## and N is the turns ration of transformer T3.
During the first portion of this half cycle of the switching period Ts, the control signals CP2', CP2' are applied to respective gates of transistors Q4, Q3 thereby driving transistor Q4 into saturation and shutting transistor Q3 off. In this condition, the charge across capacitor Ceq causes a resonant current ip1 to flow through inductor L1, substrate diode CR3 and transistor Q4 in the direction shown in FIG. 1B. This resonant current flows towards a maximum value: ##EQU3## wherein Zo is the impedance of LC circuit 14 and is defined as: ##EQU4## The resonant current will rise toward ip1.sub.max at the resonant frequency fr defined in equation (1), supra. Simultaneously, the voltage across capacitor Ceq will begin rising from -Ep towards +Ep. At time t1 (see FIG. 2), control signal CP1' is applied to the gate of transistor Q1 causing transistor Q1 to turn on. This enables the current ip2 to flow through the path illustrated in FIG. 1C and effectively adds another step function having a magnitude Es to the LC circuit 14. As a result, a second resonant current illustrated by dash lines 22 in line H of FIG. 2 will be added to the LC circuit 14. This causes the current ip2 to rise at a faster rate towards 2ip1.sub.max and causes the voltage e.sub.p across capacitor Ceq to rise at a faster rate toward the value 2Es+Ep. See lines G and H of FIG. 2.
At time t2, the voltage across capacitor Ceq will reach the value Ep at which diode bridge 20 turns on. Once diode bridge 20 begins conducting, the charging capacitor C1 is reflected back across the primary winding of transformer T3. Since the capacitance of capacitor C1 is substantially greater than the equivalent capacitor Ceq, substantially all of the current Ip3 through inductor L1 flows through the primary winding of transformer T3. This current will induce a charging current ic (see line I of FIG. 2) in the secondary winding of transformer T3. The charging current is applied both to the load Ro and to the charging capacitor C1. This current will be integrated by capacitor C1 and will charge capacitor C1 to the desired output value Eo.
Assuming that the source voltage Es and the output voltage Eo remain constant (except for ripple voltage) during the half period of the switching cycle, the voltage across capacitor Ceq will remain at a constant value Ep and all the energy (less circuit losses) flowing through inductor L1 will be transferred to charging capacitor C1 and the load Ro. As long as the voltage across capacitor Ceq remains at Ep and current continues to flow through inductor L1, energy will be transferred to capacitor C1.
At time t3, the control signal CP1' applied to the gate of transistor Q1 drops to 0 thereby turning transistor Q1 off. At that point, the current ip4 continues to flow through transistor Q3 and substrate diode CR4 as illustrated in FIG. 3D and in line H of FIG. 2. During this period, all of the energy in inductor L1 is transferred to the load Ro and to charging capacitor C1 at a decay rate of Ep/L1. When current ip4 reaches 0, substrate diode CR3 prevents the current ip from reversing thereby stopping the current flow. This, in turn, causes diode bridge 20 to stop conducting and the charging current ic falls to 0. See line I of FIG. 2. There is then a dead period t5 during which no current flows through inductor L1.
During this interval, the voltage across capacitor Ceq remains at Ep. This is the only energy left stored in the circuit and is used to reverse the polarity of the voltage across capacitor Ceq during the first portion of the next half cycle of the switching period Ts during which the transistor Q3 is on and the remaining transistors are off. See line G of FIG. 2. The operation of the converter circuit during the second half of each switching period Ts is identical to that of the first half of the cycle except the transistors Q2 and Q3 are turned on and the wave forms are inverted as shown in FIG. 2.
The foregoing circuit exhibits significant advantages over the prior art circuits as described in some detail in copending application Ser. No. 417,465. It does, however, exhibit one major drawback. Particularly, the foregoing description of the invention presumes that the diodes CR1-CR4 have a substantially instantaneous recovery time so that they immediately turn off once they are reverse biased. In fact, each diode has a predetermined reverse recovery time in which is presents substantially no resistance to a reverse current for a short period of time. When using the substrate diodes which are inherent in high-speed mosfet transistors, the reverse recovery time is relatively slow, in the order of 250 nanoseconds. During this recovery time, a phenomenon known as "shoot through" occurs wherein peak magnitude reverse currents are permitted to flow through the diodes. These peak reverse currents occur during the transition from current ip1 to ip2 and again during the transition from ip3 to ip4. Referring to FIG. 2, at the instant t1, transistor Q1 is turned on it places the source voltage Es across transistor Q1 and the diode CR3. Since the reverse resistance of diode CR3 is very low during the reverse recovery period of the diode, the total impedance in series with the power supply Es is very low. As a result, high peak currents are permitted to pass through transistor Q1 and diode CR3 during the recovery period. While these current spikes are of extremely short duration, they are sufficiently high that they destroy the transistors in the converter circuit.
A conventional technique for reducing the energy content of these "shoot through" currents is to add additional fast recovery diodes which isolate the transistor body diodes from the circuit operation. See diodes CR5-CR8 of FIG. 3. Available very fast recovery diodes reduce the shoot through time to about one-fifth of that of the power mosfet substrate diodes. While this significantly reduces the amplitude and duration of the shoot through currents (a reduction from 25 to 10 amps in a typical circuit operation), these high-speed shoot through currents creats frequency components in the 1 to 1,000 MHz range. This creates undesired noise in the system and still applies undesired excess power to the transistors.